By Dhiraj K. Pradhan, Ian G. Harris
Increase layout potency and decrease expenses with this sensible advisor to formal and simulation-based practical verification. supplying you with a theoretical and useful figuring out of the main concerns concerned, specialist authors together with Wayne Wolf and Dan Gajski clarify either formal suggestions (model checking, equivalence checking) and simulation-based suggestions (coverage metrics, try generation). You get insights into sensible matters together with verification languages (HVLs) and system-level debugging. the principles of formal and simulation-based thoughts are lined too, as are newer examine advances together with transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, together with using determination diagrams and Boolean satisfiability (SAT).
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Extra info for Practical Design Verification
The former is known as the latch-mapping problem and the latter as combinational equivalence checking (CEC). 2 Latch-mapping problem Latch mapping is the first problem to be solved when trying to check sequential equivalence of two circuits using CEC. Informally, the idea is to find a mapping of latches between the two circuits, such that under this mapping (and assuming that the circuits have the same set of input and output signals), the two circuits produce identical output sequences when supplied with the same input sequences.
In the sequel, the present- and next-state variables corresponding to a latch l will be denoted l and dl, respectively. If the two sequential circuits being checked for equivalence share the same set of inputs I, outputs O, and latches L, then it can be shown that it is sufficient to check their combinational portions for equivalence. In fact, the two sets of latches do not need to be identical, but there must be some suitable mapping between them (this notion is formalized below). Thus, in such a scenario, the sequential equivalence-checking problem can be solved as a sequence of two sub-problems: finding a mapping between the latches of the two circuits, and then checking the combinational portions of the two circuits for equivalence under this mapping.
Newk is calculated by removing the states in Reached from the states in To. 3.. The obtained Newk is set to From for the next-state enumeration. 4.. Finally, the update of Reached by the union of Reached and Newk is carried out. The implementation of the function Img(d,From) is different for explicit and implicit methods. In explicit methods, To is calculated by enumerating all possible inputs for all states in From. On the other hand, in implicit methods, a smoothing operation is carried out to calculate To.